Packaging requirements for semiconductor devices have become more stringent as the competing demands for increased functionality and smaller electronic products continue to force device manufacturers to create ever more complex package designs. In particular, increased demands for compact devices have led package manufacturers to pursue vertical integration of multiple chips to decrease the overall package size, permitting smaller final electronic products. For example, “system-in-package” designs can be created for CMOS image sensors with associated digital signal processors and memory chips. A method to electrically interconnect the chips in vertically integrated packages is by forming through-silicon vias (TSVs) through silicon chips and filling the TSVs with conductors that connect to solder bumps positioned beneath each chip.
Since a bulk of a silicon chip is electrically semi-conducting, it is required to insulate a TSV before filling it with a conductor. Similarly, a silicon surface around the TSV and on which the conductor runs is also required to be insulated. To insulate the TSV and the surrounding silicon surface, one method is to deposit a layer of silicon oxide by a process using a high temperature of around 300° C. This high-temperature process, however, affects the integrated circuit already present on the silicon chip, reducing the circuit reliability and sometimes damaging the circuit. Furthermore, this high-temperature process is rather costly. An alternative method not involving high temperature is to deposit an isolation layer, typically a polymer layer, by applying liquid polymer onto the TSV and the surrounding silicon surface, or by chemical vapor deposition (CVD) of the polymer. CVD of the polymer is particularly useful if the depth of the TSV is considerably greater than the cross-sectional width thereof. However, a problem with polymer CVD is that delamination of the polymer layer at an interface with the silicon surface or a sidewall of the TSV may occur, thereby reducing the reliability of the conductor that is deposited on the polymer layer. Delamination of the polymer layer is a result that the bonding power of polymer to silicon is not sufficient.
U.S. Pat. No. 8,049,327 discloses a method to reduce occurrence of delamination by employing a sidewall of a TSV with a scalloped surface. As a result of the use of the scalloped surface, the sidewall appears to have a number of concentric rings attached thereto. The surface area of the sidewall is thereby increased so that adhesion of a polymer layer to the sidewall is enhanced. However, the arrangement of using the scalloped surface is not directly applicable to a flat silicon surface surrounding the TSV.
A method to increase the adhesion of a polymer layer to a silicon surface is based on roughening the surface by a two-dimensional blanket etch, such as reactive ion etching (RIE), deep reactive ion etching (DRIE) and wet etching, of the silicon surface. Due to difficulty in controlling evenness of the roughening across the silicon chip, the adhesion reliability of the polymer layer is difficult to be ensured for some systems-in-packages.
There is a need in the art to have improved methods for promoting adhesion of a polymer layer or an isolation layer to a silicon surface.